In order to reduce power consumption of a semiconductor memory device and secure its reliability, power supply voltage used therein is continuously decreasing. Hence, while the power consumption has been naturally reduced, the range of voltage and current that need to be sensed by circuits or elements constituting the memory device has decreased gradually. In other words, there has been a reduction in voltage and current margins. Therefore, a need has developed for circuits or elements capable of performing, with more precision, the sensing operation and also for sensing circuits that are capable of amplifying signals to a range appropriate to be senses by their receiving circuits or elements.
In general, a typical sensing circuit used in a semiconductor memory device is a Bit Line Sense Amp (BLSA) that serves to amplify data stored in memory cells upon reading and writing operations of the device.
Due to the increase in the degree of integration of the semiconductor memory device, higher performance of the BLSA has been required. BLSA, however, needs more time to amplify the signal to a desired voltage level as the load of elements to be pulled-up or pulled-down increases. Thus amplification often may not be obtained at the desired level. In order to compensate for this, the BLSA drives its pull-up line by using an over-driving mode that employs an external voltage VEXT (a power supply voltage VDD) and a core voltage VCORE together. The BLSA elevates a voltage level of a pull-up line RTO with the external voltage VEXT (the power supply voltage VDD) higher than the core voltage VCORE and thereafter applies the core voltage VCORE to the pull-up line RTO in order to improve the amplification speed of data therein.
FIG. 1 is a circuit diagram of a bit line sensing circuit having a conventional over-driving circuit.
With reference to FIG. 1, the conventional over-driving circuit includes a core voltage supplier 10 for driving a core voltage VCORE to a pull-up line RTO of a BLSA 40, a power voltage supplier 20 for providing an external voltage VEXT (a power supply voltage VDD) to the pull-up line RTO of the BLSA 40, a discharging unit 30 for discharging the voltage provided to the pull-up line RTO of the BLSA 40, and the BLSA 40.
The conventional over-driving circuit performs an over-driving operation by always applying the same over-driving timing and external voltage VEXT thereto, regardless of whether a level of the external voltage VEXT (the power supply voltage VDD) used for over-driving the BLSA is changed to a higher voltage level High_VDD or a lower voltage level Low_VDD than a predetermined voltage level. The power supply voltage is applied to drive DRAM and generally has a voltage level of 3.3 V in SDR DRAM, 2.5 V in DDR DRAM and LPSDR, 1.8 V in DDR2 DRAM, and 2.5 V in Rambus DRAM.
In this case, if the higher voltage level High_VDD is delivered to the pull-up line RTO of the sense amp due to a change of the external voltage VEXT (the power supply voltage VDD), generation of core voltage noise VCORE Noise and increased capacitance stress of memory cells can occur. Increased current consumption can result from an unnecessarily high voltage level.
Likewise, if the lower voltage level Low_VDD is delivered to the pull-up line RTO of the sense amp due to a change of the external voltage VEXT, a greater time is needed to amplify the data stored in cells of the BLSA to a desired voltage level because the voltage level for the over-driving is not sufficient, which yields an efficiency reduction of the over-driving operation.